Cadence Allegro and OrCAD 17.20.000-2016 HF045





Cadence Allegro and OrCAD 17.20.000-2016 HF045 | 3.0 Gb


The OrCAD 17.2-2016 release introduced new capabilities for OrCAD Capture, PSpice Designer, and PCB Designer 17.2-2016 that address challenges with flex and rigid-flex design as well as mixed-signal simulation complexities in IoT, wearables, and wireless mobile devices. This latest release reduces PCB development time by addressing the need to design reliable circuits for smaller, more compact devices.


- OrCAD Flex and Rigid-Flex Technologies
To enable a faster and more efficient flex and rigid-flex design creation critical to IoT, wearables and wireless devices, the OrCAD 17.2-2016 portfolio enables several new capabilities for flex and rigid flex design to minimize design iterations. Key flex and rigid flex features include: Stack-up by zone for flex and rigid-flex designs, Inter-layer checks for rigid-flex designs, Contour and arc-aware routing.
- New Cross-Section Editor
In the OrCAD PCB Designer 17.2-2016 release, the Cross-Section Editor has been redesigned to leverage the underlying spreadsheet technology found in the Constraint Manager. It offers a one-stop shop for features that require the cross section for their setup, such as dynamic unused pad suppression and embedded component design. The Cross-Section Editor has been enhanced to support multiple stackups for rigid-flex design, each capable of supporting conductor and non-conductor layers such as Soldermask and Coverlay.

- New Padstack Editor
A new Padstack Editor has been introduced in OrCAD PCB Editor 17.2-2016 to ease padstack creation through a new modern user interface. In addition to supporting new pad geometries, drill types, additional attributes, and additional mask layers ability to define keep-outs within the padstack with complex geometries for all objects, the new capabilities allow PCB librarians to help PCB designers streamline the design process for complex padstacks, and also the commonly used padstacks.

- OrCAD PCB Designer 17.2-2016 Features
The OrCAD PCB Designer 17.2-2016 release also include new features or enhancements targeted towards improving PCB editors' productivity and ease-of-use. Other new features include: Via2via Line Fattening (HDI), Display Segments Over Voids, Layer Set Based Routing, Diff Pair Routing and DRC, Full Xnet Support, Gloss Commands, Contour Routing, and many more.

- OrCAD Capture Design Difference Viewer
The Graphical Design Difference Viewer is a powerful, real-time, design difference, visual review utility in OrCAD Capture with the ability to perform logical as well as graphical comparisons on a page-by-page basis. The Graphical Design Difference Viewer generates an interactive single-report HTML file that is platform and tool independent, a unique viewing feature to identify the differences leading to changes in circuit behavior as well as differences based on individual object level, thereby helping address the specialized needs of the users.

- Advanced Annotation
With the newly introduced Advanced Annotation feature supported by OrCAD Capture, users can assign reference ranges hierarchically by automatically assigning values and perform annotation on the whole design, on hierarchy block at any level, page and property block, giving them complete control over their component annotation process in the design cycle.

- PSpice Virtual Prototyping
The new virtual prototyping functionality introduced in PSpice helps electrical engineers overcome design challenges by automating the code generation for multi-level abstraction models written in C/C++ and SystemC. This functionality assists them in generating code requiring limited coding capabilities by design engineers and thereby making the process of virtual prototyping extremely convenient and easy.

Fixed CCRs: SPB 17.20.000-2016 HF037

1886573 ALLEGRO_EDITOR IN_DESIGN_ANA Fail to launch Sigrity executable from release 17.2-2016
1891113 ALLEGRO_EDITOR NC Clubbing total backdrill layerwise data
1886085 ALLEGRO_EDITOR SHAPE Line to Thru Via DRC is not displayed automatically
1850888 ALLEGRO_PROD_TOOLB CORE Design Compare crashes immediately after execution
1639079 ALTM_TRANSLATOR CAPTURE Title block issues with third-party design
1722577 ALTM_TRANSLATOR CAPTURE Third-party translator does not work in Capture in release 17.2-2016 if CDSROOT is not defined
1744697 ALTM_TRANSLATOR CAPTURE Third-party translator crashes
1820160 ALTM_TRANSLATOR CAPTURE Title block does not show ghost image when selecting it for placement
1628560 ALTM_TRANSLATOR PCB_EDITOR Third-party translation to PCB Editor not working properly
1836750 ALTM_TRANSLATOR PCB_EDITOR Third-party translator fails to translate a complete design
1844423 ALTM_TRANSLATOR PCB_EDITOR Third-party translation takes a long time in release 17.2-2016
1849338 ALTM_TRANSLATOR PCB_EDITOR Third-party translated board not correct
1894607 CONCEPT_HDL CORE Closing CM during 'Save Hierarchy' crashes DE-HDL
1703351 CONSTRAINT_MGR CONCEPT_HDL SigXplorer shows invalid models instead of default models in extracted topology
1868687 CONSTRAINT_MGR CONCEPT_HDL DML-independent flow: some pin-pairs missing for Differential Pair XNets when migrating 16.6 design to 17.2
1868747 CONSTRAINT_MGR CONCEPT_HDL Additional pin-pairs created on migrating design to release 17.2-2016 DML-Independent flow
1887794 CONSTRAINT_MGR OTHER Ability to disable cross-section changes in F2B flow
1859193 MODEL_EDITOR TRANSLATION DML provided by Model Integrity has a parsing error: curve must start at time zero

System Requirements: PC
Supported Operating Systems: Windows 7even or newer / 2008 Server R2 / 2012 Server
System Requirements: Cadence Allegro and OrCAD (Including EDM) version 17.20.000-2016 and above

HOMEPAGE

www.cadence.com




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